The present invention relates to resistive random access memory (ReRAM) devices. More particularly, the present invention relates to circuitry and methods for programming ReRAM devices.
ReRAM cells program by diffusion of metal ions through an electrolyte layer that is otherwise a barrier to electron flow. During programming an electric field (e-field) is presented across the device by placing appropriate potentials on the bit lines and word lines to which the cell is connected. The e-field increases until it causes breakdown of the electrolyte as the metal filament diffuses through the electrolyte from the ion source side of the device and reaches the opposite electrode. This often results in damage to the electrolyte, which makes the device difficult to erase and may even lead to device failure. A reverse e-field is applied to erase the device. The ion source of each of the ReRAM cells, throughout this document, is illustrated by the wider end.
Attempts to control this programming process have been made in some designs by placing a current limiting device on the bit line to limit the avalanche current through the ReRAM device during the programming process. FIGS. 1A through 1D are schematic diagrams showing potentials applied to a prior-art ReRAM one-transistor one ReRAM device (1T1R) memory cell 10 during program, erase, and normal operating conditions and illustrate such a prior-art solution as applied to a one-transistor one ReRAM device (1T1R) memory cell 10 such as may be employed in a programmable read only memory (PROM). ReRAM cell 10 includes a single ReRAM device 12 in series with n-channel transistor 14 and p-channel transistor 16 between bitlines 18 and 20. The output of the ReRAM cell is at an output node indicated by a dot identified by reference numeral 22. As is well known in the art bitlines 18 and 20 and the gates of transistors 14 and 16 may be selectively coupled to appropriate voltage potentials for programming, erasing, and reading the memory cell 10.
A capacitor 24 depicted in dashed lines represents the capacitance of output node 22 which is shared by many ReRAM cells. Capacitor 24 is shown only in FIGS. 1A and 1B during programming and erasing where it can present a problem to the ReRAM device itself. During read operations, the node represented by capacitor 24 must charge or discharge to the bit value before the cell can be reliably read.
P-channel transistor 16 is common to all ReRAM cells on the output node 22 and acts as a current drive/limit transistor in programming and erasing modes of FIGS. 1A and 1B. One of any number of suitable sense amplifier circuits may be coupled to output node 22 to generate a signal representing the state of the ReRAM cell from the voltage of either 0V or 0.5V that are shown in FIGS. 1C and 1D, respectively.
As shown in FIG. 1A, ReRAM device 12 is programmed to its ON state, i.e. its low resistance state, by applying a voltage such as 3.3V to the gate of n-channel transistor 14 which serves as the access transistor to enable reading and writing of ReRAM device 12. The gate of n-channel transistor 14 is biased at, for example 3.3V, and p-channel transistor 16 has a voltage Vref of, for example 2.3V placed on its gate and acts as a current limiting device that supplies a current determined by the value of Vref. Bitline 18 is biased at 3.3V and bitline 20 is biased at ground. Current controlled by p-channel transistor 16 drives through ReRAM 12 to achieve a low resistance state.
As shown in FIG. 1B, ReRAM device 12 is erased to its OFF state, i.e. its high resistance state, by applying 3.3 V to the bottom of ReRAM device 12 at bitline 20, and applying ground to the top terminal of P-channel transistor 16 at bitline 18. The gate of re-channel transistor 14 is biased at, for example 3.3V, and p-channel transistor 16 has a voltage Vref of, for example −1V placed on its gate. Current flows from bitline 20 towards bitline 18 until ReRAM device 12 exhibits a high resistance state, with n-channel transistor 14 having it source coupled to output node 22 and p-channel transistor having its drain coupled to output node 22.
After programming ReRAM device 12, during an operating mode of the 1T1R ReRAM memory cell 10, the ReRAM cell 10 is biased as shown in FIGS. 1C and 1D, with an operating voltage of, for example, 0.5V applied to bitline 18 and ground applied to bitline 20. N-channel transistor 14 is biased to be completely turned on so that in the event that ReRAM device 12 is in its ON state (FIG. 1C) ground potential appears at output node 22 and p-channel transistor 16 is biased at, for example 0V, to be turned on, so that in the event that ReRAM device is in its OFF state (FIG. 1D) output node 22 will be pulled up by p-channel transistor 16 as will be explained further below in relation to FIG. 1D. Persons of ordinary skill in the art will appreciate that the bitline capacitance 24 is not a consideration where the ReRAM cell is used as a programming element in a user-configurable circuit such as an FPGA where the memory remains in a fixed state and delay time in charging the output node for a read operation is not a consideration. With this in mind, capacitor 24 is not shown in FIGS. 1C and 1D. The operating voltage of 0.5V is chosen to minimize the stress across ReRAM device 12 in its erased (OFF) state.
This prior-art arrangement is inadequate when programming the ReRAM device as it ignores the current dump resulting from the capacitance (in dashed lines) of the output node 22. If the ReRAM device 12 is in a high resistance state, i.e. is in an erased state, its resistance is about 1 Mohm. When an applied programming voltage causes it to change to its low resistance state (e.g., 10K ohms) there will be a large current spike associated with the discharge of the capacitor 24. This large current spike can damage the structure of the ReRAM device 12.
FIG. 2 is a graph showing the voltage/current curve for a typical ReRAM device 12 during programming. The x-axis represents time from when a programming voltage is applied to change the state of ReRAM device 12 to its “low resistance” state. The left y-axis represents voltage across the ReRAM device 12 and the right y-axis represents current through the ReRAM device 12. The solid trace 26 represents voltage across the device in accordance with the prior art.
FIG. 3 is a graph that plots the power dissipated (reference numeral 28) across the ReRAM device 12 as a function of time, in accordance with the prior art, where the x-axis represents time from when the programming voltage is applied to change the state of ReRAM device 12 to its “low resistance” state, and the y-axis represents power dissipation across the ReRAM device 12. The programming voltage is initially applied at time 0. Until just prior to time 2E-08, when the capacitance 24 of the output node 22 is sufficiently discharged, a maximum amount of power, limited by the current limiting p-channel transistor 16 is dissipated. This level of power may be enough to cause damage to the ReRAM device. In the simulation shown in FIGS. 2 and 3 the voltage is applied at time zero and the filament is formed in a fraction of a nanosecond causing the current to rise to the maximum current-limited level resulting in the maximum power dissipation above that which is desired and which may be high enough to damage to the ReRAM device.